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3-volt, low noise amplifier for 0.8 C 6 ghz applications technical data MGA-85563 features ? lead-free option available ? 1.6 db minimum noise figure at 1.9 ghz ? adjustable ip3 from +12 dbm to +17 dbm via external resistor ? 18 db gain at 1.9 ghz ? single 3 v supply ? unconditionally stable applications ? amplifier for cellular, pcs, and wireless lan applications surface mount package sot-363 (sc-70) pin connections and package marking equivalent circuit (simplified) note: package marking provides orientation and identification; x is date code. description agilents MGA-85563 is an easy-to-use gaas rfic amplifier that offers low noise figure and high gain from 0.8 to 6 ghz. packaged in an ultra- miniature sot-363 package, it requires half the board space of a sot-143 package. the MGA-85563 features a minimum noise figure of 1.6 db and associated gain of 18 db at 1.9 ghz. the output is matched internally to 50 ? , and the input is partially matched, requiring only a single external inductor for optimal performance. the supply current can be adjusted using an external resistor, varying ip3 from +12 dbm to +17 dbm. the circuit uses state-of-the-art phemt technology with proven reliability. on-chip bias circuitry allows operation from a single +3 v supply, while resistive feedback ensures stability (k > 1) over frequency and temperature. r bias gnd 85x input gnd gnd output and v d 16 25 34 rf output and v d 6 4 3 1, 2, 5 r bias bias rf input ground bias attention: observe precautions for handling electrostatic sensitive devices. esd machine model (class a) esd human body model (class 0) refer to agilent application note a004r: electrostatic discharge damage and control.
2 thermal resistance [2] : ch to c = 155 c/w notes: 1. operation of this device above any one of these limits may cause permanent damage. 2. t c = 25 c (t c is defined to be the temperature at the package pins where contact is made to the circuit board). MGA-85563 absolute maximum ratings absolute symbol parameter units maximum [1] v d , max maximum device voltage v 5.5 p in cw rf input power dbm +13 t ch channel temperature c 150 t stg storage temperature c -65 to 150 electrical specifications, t c = 25 c, z o = 50 ? , v d = 3 v, and using default of no external resistor at the r bias pin symbol parameters and test conditions units min. typ. max. std. dev. [3] g test gain in test circuit [1] f = 2.0 ghz db 16 19 1.0 nf test noise figure in test circuit [1] f = 2.0 ghz db 1.85 2.3 0.1 nf min minimum noise figure f = 0.9 ghz db 1.6 (measured with opt presented to the f = 1.5 ghz 1.6 input and 50 ? presented to the output) f = 2.0 ghz 1.6 0.1 f = 2.4 ghz 1.6 f = 4.0 ghz 1.6 f = 5.0 ghz 1.6 f = 6.0 ghz 1.6 g a associated gain at nf min f = 0.9 ghz db 17.0 (measured with opt presented to the f = 1.5 ghz 17.5 input and 50 ? presented to the output) f = 2.0 ghz 18.0 1.0 f = 2.4 ghz 18.5 f = 4.0 ghz 17.5 f = 5.0 ghz 16.0 f = 6.0 ghz 14.5 ip 3 third order intercept point f = 0.9 ghz dbm 13 (measured with 50 ? presented f = 1.5 ghz 13 to the input and output) f = 2.0 ghz 11.5 1.2 f = 2.4 ghz 11.5 f = 4.0 ghz 13 f = 5.0 ghz 12.5 f = 6.0 ghz 12 p 1 db output power at 1 db gain compression f = 0.9 ghz dbm 0.8 (measured with 50 ? presented f = 1.5 ghz 0.9 to the input and output) f = 2.0 ghz 0.9 1.1 f = 2.4 ghz 1.0 f = 4.0 ghz 1.4 f = 5.0 ghz 1.3 f = 6.0 ghz 1.2
3 MGA-85563 electrical specifications, continued, t c = 25 c, z o = 50 ? , v d = 3 v, and using default of no external resistor at the r bias pin symbol parameters and test conditions units min. typ. max. std. dev. [3] vswr in input vswr [2] 2.5:1 vswr out output vswr [2] 1.3:1 isol isolation f = 0.9 C 3.0 ghz db 37 0.6 f = 3.0 C 6.0 ghz 30 i d device current ma 15 20 1.9 notes: 1. guaranteed specifications are 100% tested in the circuit of figure 1. 2. measured using the final test circuit shown below at f = 2 ghz. 3. standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. MGA-85563 final test circuit, t c = 25 c, z o = 50 ? rf input 4.7 nh 18 nh 940 pf 3 v 56 pf 56 pf rf output 85
4 MGA-85563 typical performance, t c = 25 c, z o = 50 ? , v d = 3 v, and using default of no external resistor at the r bias pin 0 1 2 4 3 012 34 6 5 noise figure (db) frequency (ghz) figure 1. minimum noise figure vs. frequency and voltage. 3.3 v 3.0 v 2.7 v 10 12 14 16 20 18 012 34 6 5 associated gain (db) frequency (ghz) figure 2. associated gain vs. frequency and voltage. 3.3 v 3.0 v 2.7 v 0 1 2 4 3 012 34 6 5 noise figure (db) frequency (ghz) figure 3. minimum noise figure vs. frequency and temperature. +85 c +25 c ?0 c 10 12 14 16 20 18 012 34 6 5 associated gain (db) frequency (ghz) figure 4. associated gain vs. frequency and temperature. +85 c +25 c 40 c 0 4 8 12 18 16 14 10 6 2 012 34 6 5 noise figure and gain (db) frequency (ghz) figure 5. gain and noise figure (50 ? source and load) vs. frequency. g a 50 nf 50 nf min -4 -2 0 2 6 4 012 34 6 5 output power (dbm) frequency (ghz) figure 6. output power @ 1 db gain compression vs. frequency and voltage. 3.3 v 3.0 v 2.7 v -4 -2 0 2 6 4 012 34 6 5 output power (dbm) frequency (ghz) figure 7. output power @ 1 db gain compression vs. frequency and temperature. +85 c +25 c 40 c 5 7 9 17 15 11 13 012 34 6 5 ip 3 (dbm) frequency (ghz) figure 8. output third order intercept point vs. frequency and voltage. 3.3 v 3.0 v 2.7 v 5 7 9 17 15 11 13 012 34 6 5 ip 3 (dbm) frequency (ghz) figure 9. output third order intercept point vs. frequency and temperature. +85 c +25 c 40 c
5 MGA-85563 typical performance, continued, t c = 25 c, z o = 50 ? , v d = 3 v, and using default of no external resistor at the r bias pin 0 4 8 12 20 16 012 34 6 5 device current, i d (ma) supply voltage (v) figure 10. device current vs. voltage and temperature. +85 c +25 c 40 c 0 4 8 12 20 16 14 18 16 22 20 26 24 32 30 28 p 1db and ip 3 (dbm) current (ma) @ 2.0 ghz figure 11. output third order intercept and p 1db vs. device current. ip 3 p 1db -10 -6 -2 2 6 4 0 -4 -8 012 34 6 5 input, ip 3 (dbm) frequency (ghz) figure 12. input third order intercept vs. frequency and device current. 31 ma 23 ma 19 ma 15 ma 0 2 4 6 10 8 012 34 6 5 vswr frequency (ghz) figure 13. input and output vswr vs. frequency. input output 15 17 19 21 25 23 14 18 16 22 20 26 24 32 30 28 gain (db) current (ma) @ 2.0 ghz figure 14. gain, |s 21 | 2 , and gain associated with minimum noise vs. current. g ass gain, |s 21 | 2
6 MGA-85563 typical scattering parameters, t c = 25 c, z o = 50 ? , v d = 3 v, and using default of no external resistor at the r bias pin freq. s 11 s 21 s 12 s 22 k ghz db mag. ang. db mag. ang. db mag. ang. db mag. ang. factor 0.2 -1.1 0.88 -10 4.0 1.6 115 -30.8 0.029 1 -4.5 0.60 -42 2.1 0.5 -1.7 0.82 -15 11.5 3.8 66 -33.6 0.021 -18 -9.8 0.32 -69 2.1 0.9 -2.1 0.79 -22 14.8 5.5 27 -35.9 0.016 -16 -15.3 0.17 -79 2.3 1.0 -2.2 0.78 -24 15.2 5.7 20 -36.5 0.015 -15 -16.2 0.16 -78 2.3 1.5 -2.2 0.77 -34 16.4 6.6 -11 -39.2 0.011 -8 -19.3 0.11 -81 2.7 1.8 -2.3 0.76 -39 16.5 6.7 -26 -41.1 0.009 5 -19.5 0.11 -88 3.5 1.9 -2.3 0.77 -41 16.6 6.7 -30 -41.3 0.009 16 -19.7 0.10 -97 3.6 2.0 -2.3 0.77 -43 16.6 6.8 -34 -41.0 0.009 26 -20.5 0.09 -110 3.4 2.1 -2.2 0.77 -45 16.8 6.9 -38 -40.3 0.010 31 -22.0 0.08 -123 3.1 2.2 -2.2 0.78 -48 16.9 7.0 -42 -39.2 0.011 34 -24.2 0.06 -136 2.8 2.3 -2.2 0.78 -50 17.1 7.0 -47 -39.2 0.011 37 -25.8 0.05 -149 2.6 2.4 -2.2 0.77 -53 17.2 7.2 -51 -39.2 0.011 39 -27.1 0.04 -164 2.5 2.5 -2.3 0.77 -55 17.3 7.3 -55 -38.4 0.012 42 -28.2 0.04 176 2.4 3.0 -2.6 0.75 -68 17.6 7.6 -78 -35.9 0.016 57 -22.4 0.08 113 1.8 3.5 -3.4 0.68 -84 17.8 7.7 -102 -31.7 0.026 61 -15.0 0.18 92 1.3 4.0 -5.4 0.54 -90 16.3 6.5 -126 -28.9 0.036 38 -10.2 0.31 51 1.4 4.5 -5.3 0.55 -96 15.7 6.1 -139 -30.2 0.031 27 -11.1 0.28 26 1.7 5.0 -5.9 0.51 -110 15.4 5.9 -156 -29.9 0.032 29 -11.1 0.28 15 1.8 5.5 -6.8 0.46 -123 15.0 5.6 -173 -29.6 0.033 26 -11.1 0.28 4 1.9 6.0 -8.2 0.39 -136 14.4 5.3 169 -28.9 0.036 25 -10.8 0.29 -7 2.0 6.5 -9.4 0.34 -150 13.8 4.9 152 -28.0 0.040 23 -10.5 0.30 -17 2.1 7.0 -10.8 0.29 -164 13.0 4.5 136 -27.1 0.044 19 -10.1 0.31 -26 2.1 7.5 -12.3 0.24 -174 12.1 4.0 120 -26.2 0.049 14 -9.8 0.33 -35 2.2 8.0 -13.5 0.21 172 11.3 3.7 106 -25.7 0.052 8 -9.4 0.34 -45 2.2 MGA-85563 typical noise parameters, t c = 25 c, z o = 50 ? , v d = 3 v, and using default of no external resistor at the r bias pin frequency f min r n (ghz) (db) mag. ang. ( ? ) 0.2 1.63 0.70 28 0.86 0.5 1.61 0.67 29 0.81 0.9 1.60 0.63 29 0.73 1.0 1.59 0.62 29 0.72 1.5 1.57 0.57 30 0.63 1.8 1.56 0.56 32 0.59 1.9 1.56 0.56 33 0.59 2.0 1.56 0.56 34 0.58 2.1 1.56 0.56 35 0.57 2.2 1.56 0.55 37 0.55 2.3 1.56 0.54 39 0.53 2.4 1.56 0.54 41 0.52 2.5 1.56 0.53 42 0.51 3.0 1.57 0.50 49 0.47 3.5 1.56 0.49 54 0.43 4.0 1.57 0.49 61 0.41 4.5 1.58 0.46 69 0.37 5.0 1.59 0.43 78 0.32 5.5 1.59 0.40 86 0.29 6.0 1.63 0.35 94 0.25 6.5 1.65 0.25 104 0.23 7.0 1.66 0.15 114 0.20 7.5 1.68 0.06 125 0.18 8.0 1.70 0.04 -48 0.15 opt
7 MGA-85563 applications information description the MGA-85563 is a two-stage, low noise gaas rfic amplifier designed for receiver applications in the 800 mhz to 5.8 ghz frequency range. the device combines low noise performance with high linearity to make it a desirable choice for receiver front end stages. a special feature of the MGA-85563 is the ability to customize its output power capability for higher linearity by setting the devices current. for applications requiring additional dynamic range, the third order intercept point can be boosted by up to 6 db by using this feature. the MGA-85563 operates from a +3-volt power supply and draws a nominal current of 15 ma. the rfic is contained in a miniature sot-363 (sc-70) package to minimize printed circuit board space. the combination of 3-volt operation and small size are important to designers of minia- ture, battery-powered wireless communications products such as cellular telephones, pcs, and rf modems. the high frequency response of the MGA-85563 extends through 6 ghz making it an excellent choice for use in 5 ghz rll as well as 2.4 and 5.7 ghz spread spectrum and ism/license-free band applications. internal, on-chip capacitors limit the low end frequency response to applications above approxi- mately 500 mhz. application guidelines the MGA-85563 is very easy to use. for most applications, all that is required to operate the MGA-85563 is to apply +3 volts to the rf output pin, and noise match the rf input. rf input to achieve lowest noise figure performance, the input of the MGA-85563 should be matched from the system impedance (typically 50 ? ) to the optimum source impedance for minimum noise, opt . since the real part of the input of the device impedance is near 50 ? and the reactive part is capacitive, a simple series inductor at the input is often all that is needed to provide a suitable noise match for many applications. rf output the rf output port is internally matched to 50 ? and will not normally require additional matching. dc bias dc bias is applied to the MGA-85563 through the rf output connection. figure 15 shows how an inductor (rfc) is used to isolate the rf signal from the dc supply. the bias line is capacitively bypassed to keep rf from the dc supply lines and prevent resonant dips or peaks in the response of the amplifier. the dc schematic for an MGA-85563 amplifier circuit is shown in figure 15. rf output rfc c3 rf input c2 +3v c1 r b 85 figure 15. schematic diagram with bias and current setting connections. a dc blocking capacitor (c2) is used at the output of the rfic to isolate the supply voltage from succeeding circuits. while the rf input terminal of the MGA-85563 is at dc ground potential, it should not be used as a current sink. if the input is connected directly to a preceding stage that has a dc voltage present, a blocking capacitor (c1) should be used. setting the bias current for higher linearity the MGA-85563 has a feature that allows the user to place an external resistor (r b ) from the r bias pin to dc ground and thereby increase the device current. the current can be raised from its nominal 15 ma up to approximately 50 ma. the higher current increases amplifier linearity by boosting output power (p 1db ) by up to 8 db. maximum linearity performance is obtained at a current of 30 to 35 ma. currents greater than 35 ma are not recommended since the output power has reached a point of diminishing returns at this current. figure 16 shows the relationship between device current and the value of the external resistor.
8 10 15 20 25 35 30 10 50 90 130 170 200 i d (ma) r b ( ? ) figure 16. bias current vs. resistor value. the current is increased only in the second stage of the MGA-85563. bias current for the first stage remains fixed and thus the input impedance and noise figure for the amplifier are unaffected by the increase in bias current. the output match is also generally unaffected by increased device current and remains quite good over the complete operating current and frequency range. pcb layout a recommended pcb pad layout for the miniature sot-363 (sc-70) package that is used by the MGA-85563 is shown in figure 17. 0.026 0.079 0.018 0.039 dimensions in inches. figure 17. recommended pcb pad layout for agilent s sc70 6l/sot-363 products. this layout provides ample allowance for package placement by automated assembly equip- ment without adding parasitics that could impair the high fre- quency rf performance of the MGA-85563. the layout is shown with a footprint of a sot-363 package superimposed on the pcb pads for reference. starting with the package pad layout in figure 17, an rf layout similar to the one shown in figure 18 a good starting point for microstripline designs using the MGA-85563 amplifier. rf input rf output r b 85 figure 18. rf layout. adequate grounding of pins 1, 2, and 5 of the rfic are important to maintain device stability and rf performance. each of the ground pins should be connected to the groundplane on the back- side of the pcb by means of plated through holes (vias). the ground vias should be placed as close to the package terminals as practical. at least one via should be located next to each ground pin to assure good rf grounding. it is a good practice to use multiple vias to further minimize ground path inductance. if the adjustable current feature is to be used, an additional ground pad located near the r bias pin may be used to connect the current- setting resistor (r b ) directly from the r bias pin to ground. (the ground pad for pin 5 could also be used for this purpose.) note that when using an external resistor, the r bias pad should not be bypassed to ground. doing so could result in undesirable resonances in the amplifier gain response. if for any reason the r b resistor is not located immediately adjacent to the MGA-85563 (such as in the case of remote current adjust- ment or to implement dynamic control of the devices linearity), then a small series resistor (e.g., 10 ? ) should be located near the r bias pin to de-q the connection from the MGA-85563 to the external current-setting circuit. if the adjustable current feature of the MGA-85563 is not used, the r bias pin should be left open. when not used, the pcb pad for the r bias pin should only be large enough to provide a mechanical attachment, such as shown in figure 17. if a large pad or length of line is connected to the r bias pad, a potential exists for the pad parasitics to interact with the internal circuitry of the MGA-85563 to create an undesir- able resonance in the gain response of the amplifier. while it might be considered an effective rf practice, it is recom- mended that the pcb pads for the ground pins not be connected together underneath the body of the package. in many cases, it is important that the individual stages within the device be grounded separately to prevent inadvertent interstage feedback. in addition, pcb traces hidden under the package cannot be adequately inspected for smt solder bridging or quality.
9 pcb materials fr-4 or g-10 type materials are good choices for most low cost wireless applications using single or multi-layer printed circuit boards. typical single-layer board thickness is 0.020 to 0.031 inches. circuit boards thicker than 0.031 inches are not recom- mended due to excessive inductance in the ground vias. for noise figure critical or higher frequency applications, the additional cost of ptfe/glass dielectric materials may be warranted to minimize transmis- sion line loss at the amplifiers input. application example the printed circuit layout in figure 19 can be used with the MGA-85563 for frequencies from 800 mhz through 6 ghz. this layout is a microstripline design (solid groundplane on the back- side of the circuit board) with 50 ? interfaces for the rf input and output. the circuit is fabri- cated on 0.031-inch thick fr-4 dielectric material. plated through holes (vias) are used to bring the ground to the top side of the circuit where needed. multiple vias are used to reduce the inductance of the paths to ground. in out r bias +v d mga-85-a figure 19. multi-purpose pcb layout. 1.9 ghz design to illustrate the simplicity of using the MGA-85563, a 1.9 ghz amplifier for pcs type receiver applications is presented. to achieve minimum noise figure, the 50 ? input to the amplifier is matched to opt . from the table of typical noise parameters, the value of opt at 1.9 ghz is found to be 0.56 +33 . the conjugate of opt , 0.56 -33 , is plotted on the smith chart as point a in figure 20. the addition of a 0.108 inch length (actual length on fr-4; electrical length is 11.7 of 50 ? transmission line (mlin) rotates point a around to the r = 1 circle on the smith chart. a series 5.6 nh inductor (l1) is then all that is required to complete the match to 50 ? . a 1 c a ( opt ) b 2 -2 b 0.5 0.5 0.2 -0.2 0.2 2 -0.5 -1 mlin rf input c (50 ? ) l1 figure 20. input impedance match. the output of the MGA-85563 is already well matched to 50 ? and no additional matching is needed. the resulting rf circuit is shown in figure 21. 5.6 nh 50 ? 0.108 in. rf output mga- 85563 rf input figure 21. input circuit for 1.9 ghz. a schematic diagram of the complete 1.9 ghz circuit with the input noise match and dc biasing is shown in figure 22. rfc rf input c4 c3 v d 85 rf output notes: l1 = 5.6 nh rfc = 22 nh c1 c4 = 56 ph mlin = 0.108 inch, 50 ? (c1, c4 and r b are optional) l1 c1 c2 mlin r b figure 22. schematic of 1.9 ghz circuit. dc bias is applied to the MGA-85563 through the rfc at the rf output pin. the power supply connection is bypassed to ground with capacitor c3. provi- sion is made for an additional bypass capacitor, c4, to be added to the bias line near the +3 volt connection. c4 will not normally be needed unless several stages are cascaded using a common power supply. the optional resistor, r b , may be added if desired to increase device current to handle higher level signals. the use of the bias- setting resistor will not affect the input matching circuit. since the input terminal of the MGA-85563 is at ground potential, the input dc blocking capacitor c1 need not be used unless the amplifier is connected to a preceding stage that has a voltage present at this point. the value of the dc blocking and rf bypass capacitors (c1 C c4) should be chosen to provide a small reactance (typically <2 ohms) at the lowest operating frequency. for this 1.9 ghz design example, 56 pf capacitors with a reactance of 1.5 ohms are adequate. the reactance of the rf choke (rfc) should be high
10 (i.e., several hundred ohms) at the lowest frequency of opera- tion. a 22 nh inductor with a reactance of 262 ohms at 1.9 ghz is sufficiently high to minimize the loss from circuit loading. the completed 1.9 ghz amplifier for this example with all compo- nents and sma connectors assembled is shown in figure 23. designs for other frequencies the same basic design approach described above for 1.9 ghz can be applied to other frequency bands. inductor values for matching the input for low noise figure are shown in table 1. for frequencies below 1000 mhz, the series input inductor approach provides a good match but may not completely noise match the MGA-85563. a two- element matching circuit may be required at lower frequencies to exactly match the input to opt . at lower frequencies, the real part of opt has started to move away from 50 ? (i.e., away from the r = 1 circle on the smith chart) as the angle of opt decreases. a small shunt capacitor (typically 0.4 to 0.9 pf) added between the input pin and the adjacent ground pad to create a shunt c-series l matching network will realize an improvement in noise figure of several tenths of a db. a lower value for l1 may be needed depending on the actual length of the input line between pin 1 and l1 as well as the value of the shunt c. for frequencies above 3 ghz, the input is already well matched to 50 ? and no additional matching is normally needed. frequency l1 (ghz) (nh) 0.8* 22 0.9* 18 1.5 8.2 1.9 5.6 2.4 2.7 5.1 0 5.8 0 table 1. input inductor values for various operating frequencies. (*additional matching required for optimum nf). actual component values may differ slightly from those shown in table 1 due to variations in circuit layout, grounding, and component parasitics. a cad program such as agilents touch- stone ? is recommended to fully analyze and account for these circuit variables. hints and troubleshooting oscillation unconditional stability of the MGA-85563 is dependent on having very good grounding. inadequate device grounding or poor pcb layout techniques could cause the device to be potentially unstable. even though a design may be unconditionally stable (k > 1 and b1 > 0) over its full frequency range, other possibilities exist that may cause an amplifier circuit to oscillate. one thing to check is feedback in bias circuits. it is important to capacitively bypass the connections to active bias circuits to ensure stable operation. in multistage circuits, feedback through bias lines can also lead to oscillation. components of insufficient quality for the frequency range of the amplifier can sometimes lead to instability. also, component values that are chosen to be much higher in value than is appropri- ate for the application can present a problem. in both of these cases, the components may have reactive parasitics that make their impedances very different than expected. chip capacitors may have excessive inductance, or chip inductors can exhibit resonances at unexpected frequencies. c4 c3 rfc l1 mlin in out r bias +v d mga-85-a c2 85 figure 23. complete 1.9 ghz amplifier circuit.
11 a note on supply line bypassing multiple bypass capacitors are normally used throughout the power distribution within a wireless system. consideration should be given to potential resonances formed by the combi- nation of these capacitors and the inductance of the dc distribution lines. the addition of a small value resistor in the bias supply line between bypass capacitors will often de-q the bias circuit and eliminate resonance effects. statistical parameters several categories of parameters appear within this data sheet. parameters may be described with values that are either minimum or maximum, typical, or standard deviations. the values for parameters are based on comprehensive product characterization data, in which automated measurements are made on of a minimum of 500 parts taken from three non- consecutive process lots of semiconductor wafers. the data derived from product character- ization tends to be normally distributed, e.g., fits the standard bell curve. parameters considered to be the most important to system perfor- mance are bounded by minimum or maximum values. for the MGA-85563, these parameters are: gain (g test ), noise figure (nf test ), and device current (i d ). each of the guaranteed param- eters is 100% tested as part of the manufacturing process. values for most of the parameters in the table of electrical specifi- cations that are described by typical data are the mathematical mean ( ), of the normal distribu- tion taken from the characteriza- tion data. for parameters where measurements or mathematical averaging may not be practical, such as s-parameters or noise parameters and the performance curves, the data represents a nominal part taken from the center of the characterization distribution. typical values are intended to be used as a basis for electrical design. to assist designers in optimizing not only the immediate amplifier circuit using the MGA-85563, but to also evaluate and optimize trade-offs that affect a complete wireless system, the standard deviation ( ) is provided for many of the electrical specifica- tions parameters (at 25 c) in addition to the mean. the stan- dard deviation is a measure of the variability about the mean. it will be recalled that a normal distribu- tion is completely described by the mean and standard deviation. standard statistics tables or calculations provide the probabil- ity of a parameter falling between any two values, usually symmetri- cally located about the mean. referring to figure 24 for ex- ample, the probability of a parameter being between 1 is 68.3%; between 2 is 95.4%; and between 3 is 99.7%. 68% 95% 99% parameter value mean ( ) (typical) -3 -2 -1 +1 +2 +3 figure 24. normal distribution. phase reference planes the positions of the reference planes used to specify s-param- eters and noise parameters for the MGA-85563 are shown in figure 25. as seen in the illustra- tion, the reference planes are located at the point where the package leads contact the test circuit. reference planes test circuit figure 25. phase reference planes. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-363 package, will reach solder reflow temperatures faster than those with a greater mass. the MGA-85563 is qualified to the time-temperature profile shown in figure 26. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evapo-
12 rating solvents from the solder paste. the reflow zone briefly elevates the temperature suffi- ciently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool- down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. the maximum temperature in the reflow zone (t max ) should not exceed 235 c. these parameters are typical for a surface mount assembly process for the MGA-85563. as a general guideline, the circuit board and components should be exposed time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 figure 26. surface mount assembly profile. only to the minimum tempera- tures and times necessary to achieve a uniform reflow of solder. electrostatic sensitivity rfics are electro- static discharge (esd) sensitive devices. although the MGA-85563 is robust in design, permanent damage may occur to these devices if they are sub- jected to high energy electrostatic discharges. electrostatic charges as high as several thousand volts (which readily accumulate on the human body and on test equip- ment) can discharge without detection and may result in degradation in performance, reliability, or failure. electronic devices may be subjected to esd damage in any of the following areas: ? storage & handling ? inspection & testing ? assembly ? in-circuit use the MGA-85563 is a esd class 1 device. therefore, proper esd precautions are recommended when handling, inspecting, testing, assembling, and using these devices to avoid damage.
13 package dimensions outline 63 (sot-363/sc-70) part number ordering information no. of part number devices container MGA-85563-tr1 3000 7" reel MGA-85563-tr2 10000 13" reel MGA-85563-blk 100 antistatic bag MGA-85563-tr1g 3000 7" reel MGA-85563-tr2g 10000 13" reel MGA-85563-blkg 100 antistatic bag note: for lead-free option, the part number will have the character g at the end. e he d e a1 b a a2 q1 l c dimensions (mm) min. 1.15 1.80 1.80 0.80 0.80 0.00 0.10 0.15 0.10 0.10 max. 1.35 2.25 2.40 1.10 1.00 0.10 0.40 0.30 0.20 0.30 symbol e d he a a2 a1 q1 e b c l notes: 1. all dimensions are in mm. 2. dimensions are inclusive of plating. 3. dimensions are exclusive of mold flash & metal burr. 4. all specifications comply to eiaj sc70. 5. die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. package surface to be mirror finish. 0.650 bcs
tape dimensions and product orientation for outline 63 device orientation p p 0 p 2 f w c d 1 d e a 0 10 max. t 1 (carrier tape thickness) t t (cover tape thickness) 10 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.10 4.00 0.10 1.75 0.10 0.061 + 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 + 0.30 - 0.10 0.254 0.02 0.315 + 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.40 0.10 0.062 0.001 0.205 + 0.004 0.0025 0.0004 cover tape user feed direction cover tape carrier tape reel end view 8 mm 4 mm top view 85x 85x 85x 85x for product information and a complete list of agilent contacts and distributors, please go to our web site. www.agilent.com/semiconductors e-mail: semiconductorsupport@agilent.com data subject to change. copyright ? 2004 agilent technologies, inc. obsoletes 5968-6303e november 16, 2004 5989-1799en

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